(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of providing Electro Static Discharge protection as part of packaging a flip chip.
(2) Description of the Prior Art
Flip chip technology is a technique whereby interconnections are made between a first array of contact points provided over an active surface of a semiconductor chip and a second array of contact points provided over the surface of a flip chip supporting substrate. Typically, solder bumps are provided as terminals over the active surface of the flip chip, these solder bumps are aligned and bonded with contact pads provided over the surface of a substrate that serves as a semiconductor device mounting support.
Flip chip bonding provides advantages of a reduction in the interconnection length, a smaller package footprint and allows for a lower package profile when compared with conventional wire bond packages. Flip chip technology is not being limited to providing points of I/O interconnect of the mounted chip in accordance with a particular pattern or array. This technology can therefore provide points of I/O interconnect across the entire active surface of the mounted device and allows for significantly extending input/output capabilities of the mounted chip. The limitation that is in this case as yet in effect is a limitation of pitch or spacing between the points of electrical contact that are created over the joining surfaces.
One of the methods that has been employed for mounting semiconductor devices over a supporting substrate comprises the use of Ball Grid Array (BGA) contact points. In using BGA contact points a pattern of closely spaced contact balls is used over the active surface of the chip to provide interconnections between the flip chip and a supporting, frequently ceramic based, substrate. This approach, while allowing for an extension of I/O capabilities, presents problems of contact ball and solder joint reliability. This latter problem is greatly exacerbated by the impact of thermal cycling during the creation of the semiconductor device package and by excessive mechanical stress that is exerted on one or more of the applied contact balls due to lack of planarity of the interfacing points of contact.
One of the aspects of semiconductor packaging is the occurrence of Electro Static Discharge (ESD) whereby seemingly randomly acquired electric charges are released over a path of least resistance. The main source of the accumulation of the high voltage that results in an ESD is tribo-electricity, which is electricity that is caused by frictional rubbing between two contacting surfaces. Typically, ESD can result in a voltage peak of about 2,000 volts or more, which can result in a discharge of a current of about 1.5 amperes over a resistance of about 1,500 ohms.
The ESD can, due to its unpredictable nature and also due to the amount of discharge that can take place, result to device damage and must therefore by controlled or prevented. The invention addresses this concern and provides protection against ESD effects by providing a ESD network that results in controlled ESD without thereby damaging packaged flip chips.
U.S. Pat. No. 5,970,321 (Hively et al.) shows a flip-chip and ESD design.
U.S. Pat. No. 6,144,542 (Ker et al.) reveals ESD bus protection.
U.S. Pat. No. 6,078,068 (Tamura) shows an ESD bus/die edge seal.